Framework and Tools for Run-Time Recon gurable Designs

This paper describes a framework and tools for automating the production of designs that can be partially recon gured at run time. The approach involves several stages, including: (i) a partial evaluation stage, which produces con guration les for a given design, where the number of con gurations are minimised during the compile-time sequencing stage; (ii) an incremental con guration calculation stage, which takes the output of the partial evaluator and generates an initial con guration le and incremental con guration les that partially update preceding con gurations; (iii) an optimisation stage for devices or systems supporting simultaneous conguration of multiple components. While many of our techniques are independent of the design language and device used, experimental tools have been developed that target Xilinx 6200 devices. Simultaneous con guration, for example, can be used to reduce the time for recon guring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst. Our tools have been used in developing a variety of designs, including arithmetic, video and database applications.